In digital systems with corresponding clock speed rates, a clock signal plays a very important role, besides determining the performance of the system, it is closely related to an electricity usage. Since mobile solutions are popular, most PC CPUs, digital signal processors (DSP) and miniature controlling units have steadily lowered their power consumption to achieve a goal of saving electricity. During times of inactivity of the controlling units, the system is switched to a state of a lower work frequency.
For normal traditional frequency dividing installations, please refer to FIG. 1A. It usually comprises one n-bit D Flip Flop (DFF) together with one adder. This structure gives a different frequency signal after the frequency lowering process, which is then imported into the D Flip Flop. For this means, the system also has to make use of a multiplexer, which uses the control signal FREQ_SEL to select the target frequency signal, then outputs this target frequency signal. During the layout, the positions of each D Flip Flop are different; therefore the process of transporting output to the multiplexer often produces different delays. At the same time, when the frequency selecting control signal FREQ_SEL changes the frequency, because the control signals arrive at different times, short change to a frequency differing from the target frequency takes place. Naturally, over a period of time the signal will eventually change to the target signal, but under certain circumstances, this could have a large impact on the procedures. As an example, please refer to the clock diagram of FIG. 1B. At a time of approximately 215 ns, the control signal FREQ_SEL has three bits changed from §000″ to §011″. Because the delays of the three bits, the FREQ_SEL signal do not correspond, the FREQ_SEL first changes from §000″ to §010″, then , 0.2 ns later, it changes to a stable position of §011″. Thus is causes the CLKOUT to create a tiny pulse signal, which is also called a glitch signal. Because of this, the system might take false actions.
For another type of a traditional frequency divider, please refer to the binary up counter on FIG. 2A. Any possible number of cycles can be used for the input COUNT_TO, as well as making use of it's a count to flag (TERCNT), and at the determined COUNT time, a CLKIN cycle pulse signal will be created. As shown on FIG. 2B, if this pulse signal is used as a clock, it has a disadvantage that the duty cycle produced is not necessarily 50%—50%, furthermore there is the possibility of an occurrence of a glitch signal.
The programmable frequency divider presented by this invention makes use of the method of controlling the input adjustment parameters, which can result in a clock frequency divided by 2m (with m being a integer of zero or above), with no possibility of an occurrence of an clock glitch signal, thus providing a lower working clock for the controlling unit.